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King Billion Electronics Co., Ltd

HE84G770
HE80004H SERIES
- Table of Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. 9.1. 9.2. 9.3. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 21.1. 21.2. 21.3. General Description ___________________________________________________________________3 Features _____________________________________________________________________________3 Functional Block Diagram ______________________________________________________________4 Pin Description _______________________________________________________________________4 Pad Diagram _________________________________________________________________________7 ROM Map Configurations_____________________________________________________________11 External RAM/Flash Memory__________________________________________________________14 LCD Display RAM Map ______________________________________________________________15 LCD driver configurations_____________________________________________________________16 16 Gray Scale LCD Display RAM Map ________________________________________________17 4 Gray Scale LCD Display RAM Map _________________________________________________23 Black and White LCD Display RAM Map______________________________________________26 LCD Power Supply_________________________________________________________________29 Oscillators ________________________________________________________________________32 General Purpose I/O _______________________________________________________________33 Key Scan Circuit___________________________________________________________________35 Timer1 ___________________________________________________________________________37 Timer2 ___________________________________________________________________________38 Time Base ________________________________________________________________________39 Watch Dog Timer __________________________________________________________________39 Voice Output ______________________________________________________________________41 Low Voltage Detection/Reset _________________________________________________________46 Infrared output____________________________________________________________________47 Universal Asynchronous Receiver/Transmitter__________________________________________48 Interface Registers _________________________________________________________________49 Baud Rate Configuration Register ____________________________________________________49 Interrupt Enable, Identification Register ______________________________________________50
October 31, 2003
1
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
21.4. 21.5. 22. 23. 24. 25. 26. 27. 28. 29.

HE84G770
HE80004H SERIES
Line Control Register_______________________________________________________________51 Line Status Register ________________________________________________________________52 Extension Register Access ___________________________________________________________53 Summary of Registers and Mask Options ______________________________________________53 Absolute Maximum Rating __________________________________________________________57 Recommended Operating Conditions _________________________________________________57 AC/DC Characteristics _____________________________________________________________57 Application Circuit_________________________________________________________________59 Important Note ____________________________________________________________________61 Updated History ___________________________________________________________________61
October 31, 2003
2
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd

HE84G770
HE80004H SERIES
1. General Description
HE84G770 is a member of 8-bit Micro-controller series developed by King Billion Electronics. External address and data buses are provided to access external memory. This chip has 6400 pixel, 16 gray-scale LCD driver built-in with 4 different configurations, and up to 36-bit general purpose I/O ports. The built-in OP comparator can be used with light, voice, temperature and humility sensor or used to detect the battery low. The 8-bit current-type D/A converter and PWM driver output provides the complete speech output solutions. The 1M bytes ROM and 6K bytes RAM can be used for the storage of large speech data, image and text, etc. An UART is included to provide the serial communication capability. IR output makes it suitable for remote control applications. The instruction sets of HE80004H series is easy to learn and simple to use. There are only thirty-two instructions and four addressing modes. Most of instructions take only 3 oscillator clocks to complete. The performance and low power consumption make it suitable for battery-powered applications such as translator, data bank, educational toy, digital voice recorder, etc.
2. Features
2.4V ~ 3.6V Fast clock: 32768 Hz ~ 8 MHz Slow clock: 32768 Hz Four Operation Modes: Fast, Slow, Idle, Sleep modes. Internal ROM: 1M Bytes (512K Byte Program ROM, 512K Byte Data ROM) Internal RAM: 6K Bytes (Shared with LCD RAM). 6 ~ 36 bit Bi-directional general purpose I/O port with push-pull or open-Drain output type selectable for each I/O pin by mask option. Up to 6400 pixels with 16, 4 gray-scale or Black/White LCD driver. Segment extender interface with KDGS80. 4 LCD configurations: [32 x 128], [48 x 112], [64 x 96], [80 x 80]. Built-in LCD power supply with input power regulator, voltage multiplier circuit and bias generating circuit. PWM output. 8-bit current-type DAC output. Built-in OP comparator. Built-in UART for serial communication. IR output. Low voltage reset: 2.2V Low voltage detection: 2.4V, 2.6V, 2.8V and 3.0V Built-in keyboard auto scan hardware for up to 4x20 key matrix (shared with LCD SEG pins) not only reduces the hardware cost, but also reduces the firmware effort. Watchdog timer. Two 16-bit timers and one time-base timer. Two external interrupts, three internal timer interrupts and one internal UART interrupt. Instruction set: 32 instructions, 4 addressing modes. Operation Voltage: Dual Clock System:
October 31, 2003
3
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 U14
COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5
Pin Name COM[31..0] LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A
LCAP?A, LCAP?B, VR12 PRTC, PRTD PRT14, PRT15, PRT17 OLFR, OCCK SEGD, SEGA SEG COM LVL[5..1], LGS1, LVREG SIN, SOUT
4. Pin Description
3. Functional Block Diagram
October 31, 2003

LCD Driver
LCD Power Supply
Segment Ext. Interface
Ext. Memory Interface
I/O Port
UART

I/O O LCD COMMON Driver pads. O Charge Pump Capacitor Pin. O Charge Pump Capacitor Pin. O Charge Pump Capacitor Pin. O Charge Pump Capacitor Pin. O Charge Pump Capacitor Pin. O Charge Pump Capacitor Pin.
HE84G770
TC2
TC1
TB
8 Bit CPU
1 MB ROM
6 KB RAM
WDT
LVR LVD
King Billion Electronics Co., Ltd
4 OP Amp IR
IRO OPO, OPIN, OPIP

Description

Fast Clock OSC.
Slow Clock OSC
PWM
DAC
VO, DAO
PWM
SXI, SXO
FXI, FXO
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 SEG[0]/PRT17[0] SEG[1]/PRT17[1] SEG[2]/PRT17[2] SEG[3]/PRT17[3] SEG[4]/PRT17[4] SEG[5]/PRT17[5] SEG[6]/PRT17[6] SEG[7]/PRT17[7] SEG[8]/PRT15[0] SEG[9]/PRT15[1] SEG[10]/PRT15[2] SEG[11]/PRT15[3] SEG[12]/PRT15[4] SEG[13]/PRT15[5] SEG[14]/PRT15[6] SEG[15]/PRT15[7] SEG[16]/PRT14[0] SEG[17]/PRT14[1] SEG[18]/PRT14[2] SEG[19]/PRT14[3] SEG[20]/PRT14[4] SEG[21]/PRT14[5] SEG[22]/PRT14[6] SEG[23]/PRT14[7] SGKY24 SGKY25 SGKY26 SGKY27 SGKY28 SGKY29 SGKY30 SGKY31 SGKY32 SGKY33 SGKY34 SGKY35 SGKY36 SGKY37 SGKY38 SGKY39 SGKY40 SGKY41 SGKY42 SGKY43 SEG44/CS1 SEG45/CS0 SEG46/WE SEG47/OE SEG48/A[0] SEG49/A[1] SEG50/A[2] SEG51/A[3] SEG52/A[4] SEG53/A[5] SEG54/A[6] SEG55/A[7] SEG56/A[8] SEG57/A[9] SEG58/A[10] SEG59/A[11] SEG60/A[12] SEG61/A[13] SEG62/A[14] SEG63/A[15] SEG64/A[16] SEG65/A[17] SEG66/A[18] SEG67/A[19] SEG68/A[20] SEG69/A[21] SEG70/A[22] SEG71/A[23] SEG72/D[0] SEG73/D[1] SEG74/D[2] SEG75/D[3] SEG76/D[4] SEG77/D[5] 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132
COM4 COM3 COM2 COM1 COM0 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A LVL5 LVL4 LVL3 LVL2 LVL1 LGS1 LVREG VR12 GND VO DAO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P SXO SXI VX OLFR OCCK VDD PRTD[7]/INT2//WKUP[5] PRTD[6]/INT1/WKUP[4] PRTD[5]/WKUP[3] PRTD[4]/WKUP[2] PRTD[3]/WKUP[1] PRTD[2]/WKUP[0] PRTD[1]/SIN PRTD[0]/SOUT GND_PWM PWM IRO CS3 CS2 VDD_RAM PRTC[7]/SCNI[3] PRTC[6]/SCNI[2] PRTC[5]/SCNI[1] PRTC[4]/SCNI[0] CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60
SEG78/D[6] SEG79/D[7] CMSG79 CMSG78 CMSG77 CMSG76 CMSG75 CMSG74 CMSG73 CMSG72 CMSG71 CMSG70 CMSG69 CMSG68 CMSG67 CMSG66 CMSG65 CMSG64 CMSG63 CMSG62 CMSG61
131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G770
HE80004H SERIES
Version:V1.1
King Billion Electronics Co., Ltd
Pin Name LCAP1A LVL5 LVL4 LVL3 LVL2 LVL1 LGS1

HE84G770
HE80004H SERIES
I/O Description O Charge Pump Capacitor Pin. P LCD Bias Voltage 5. P LCD Bias Voltage 4 P LCD Bias Voltage 3 P LCD Bias Voltage 2 P LCD Bias Voltage 1. I Regulator Voltage Setting Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns pumped LVREG O to LVL5. Adjust resistor between LGS1 and LVREG to set LVREG voltage. VR12 I Charge Pump Input. The buffered output of the fine-adjusted VREG. GND P Power Ground Input. VO O DAC Output. DAO O Alternate output of DAC. OPIN I Inverting input of OP Amp. OPIP I Non-inverting input of OP Amp. OPO O Output of OP Amp. RSTP_N I System Reset Input Pin. Level trigger, active low on this pin will put the chip in reset state. External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (`0' for RC FXO, O, type and `1' for crystal type). For RC type oscillator, one resistor needs to be connected FXI B between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI and FXO. Please refer to application for details. Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for TSTP_P I improving ESD, please connect this point with zero Ohm resistor to GND. External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base SXO, O, and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type SXI I can be selected by mask option MO_SXTAL. Choose `0' for RC type and `1' for crystal oscillator. Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in VX I application circuit. OLFR O LCD frame signal for interfacing with LCD segment extender KDGS80. OCCK O LCD data load pin for interfacing with LCD segment extender KDGS80. Positive power Input. A 0.1 F decoupling capacitors should be placed as close to IC VDD VDD P and GND pads as possible for best decoupling effect. 8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask option MO_DPP[7..0] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as PRTD[7..2] PRTD[1]/SIN B input, `1' must be outputted before reading the pin. PRTD[0]/SOUT PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources. PRTD[1] shares pad with UART Receiver SIN pin. PRTD[0] shares pad with UART transmitter SOUT pin. GND_PWM O Dedicated Ground for PWM output. The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to PWM O turn on PWM. Using VDD & PWM to drive output device. IRO O The Infrared output. 4-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask option MO_CPP[7..4] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as PRTC[7..4]/ B SCNI[3..0] input, `1' must be outputted before reading the pin. PRTC[7..4] is shared with Key Scan Dedicated Input SCNI[3..0]. The Key Scan function can be disabled by clearing MO_LCDKEY mask option to `0'. VDD_RAM P Dedicated power input for RAM CMSG[32..79] O COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to be
October 31, 2003
5
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Pin Name SEG[79..72]/ D[7..0] SEG[71..48]/ A[23..0] OE/SEG[47] I/O

HE84G770
HE80004H SERIES
Description COM drivers or SEG drivers can be selected by mask option MO_COM[1..0]. Please refer to LCD driver configuration for details. LCD segment SEG[71..48] outputs share pads with address bus A[23..0] of external memory. Output Enable control of external memory shares pad with SEG[47]. The function of the pin is selected by mask option MO_ EXMEM. When used as Output Enable control pin, this pin control the tri-state buffer of external memory data bus. Write Enable 0 of external memory shares pad with SEG[46]. The function of the pin is selected by mask option MO_ EXMEM. When used as Write Enable control pin, this pin controls Write Enable input of the external memory device. Chip Enable 0 of external memory shares pad with SEG[45]. The function of the pin is selected by mask option MO_ EXMEM. When used as Chip Enable control pin, this pin select or de-select the external memory device based on the address been accessed. Chip Enable 1 of external memory shares pad with SEG[44]. The function of the pin is selected by mask option MO_ EXMEM. When used as Chip Enable control pin, this pin select or de-select the external memory device based on the address been accessed. Chip Enable 2 of external memory. This pin select or de-select the external memory device based on the address been accessed. Chip Enable 3 of external memory. This pin select or de-select the external memory device based on the address been accessed. LCD segments share pads with key scan out SCNO[19..0]. The key scan function of these pins can be disabled by mask option clearing MO_LCDKEY to `0', then SGKY[43..24] function as LCD segment driver only. Setting MO_LCDKEY to `1' will turn on the key scan function. 8 bits bi-directional I/O port 14 are shared with LCD segment pads SEG[23..16]. The function of the pad can be selected individually by mask options MO_LIO14[7..0]. (`1' for LCD and `0' for I/O). The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, "1" must be outputted before reading. 8 bits bi-directional I/O port 15 are shared with LCD segment pads SEG[15..8]. The function of the pad can be selected individually by mask options MO_LIO15[7..0]. (`1' for LCD and `0' for I/O). The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, "1" must be outputted before reading. 8 bits bi-directional I/O port 17 are shared with LCD segment pads SEG[7..0]. The function of the pad can be selected individually by mask options MO_LIO17[7..0]. (`1' for LCD and `0' for I/O). The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, "1" must be outputted before reading.
O LCD segment SEG[79..72] outputs share pads with data bus D[7..0] of external memory. O O
WE/SEG[46]
O
CS0/SEG[45]
O
CS1/SEG[44] CS2 CS3 SGKY[43..24]
O O O O
PRT14[7..0]/ SEG[23..16]
B/ O
PRT15[7..0]/ SEG[15..8]
B/ O
PRT17[7..0]/ SEG[7..0]
B/ O
October 31, 2003
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Version:V1.1
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King Billion Electronics Co., Ltd

HE84G770
HE80004H SERIES
5. Pad Diagram
October 31, 2003
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Version:V1.1
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King Billion Electronics Co., Ltd
Pin No. Name

Pin No.
Name
HE84G770
HE80004H SERIES
Y Coordinate
X Coordinate
Y Coordinate
X Coordinate
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A LVL5:P
-5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -5265 -4814.02 -4688.62 -4563.22 -4437.82 -4312.42 -4185.02 -4059.62 -3934.22 -3808.82 -3683.42 -3558.02 -3432.62 -3307.22
1623.1 1497.7 1372.3 1246.9 1121.5 996.1 870.7 745.3 619.9 494.5 369.1 243.7 118.3 -7.1 -132.5 -257.9 -383.3 -508.7 -634.1 -759.5 -884.9 -1010.3 -1135.7 -1261.1 -1386.5 -1511.9 -1637.3 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 8
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
CMSG[56] CMSG[57] CMSG[58] CMSG[59] CMSG[60] CMSG[61] CMSG[62] CMSG[63] CMSG[64] CMSG[65] CMSG[66] CMSG[67] CMSG[68] CMSG[69] CMSG[70] CMSG[71] CMSG[72] CMSG[73] CMSG[74] CMSG[75] CMSG[76] CMSG[77] CMSG[78] CMSG[79] SEGD[79] SEGD[78] SEGD[77] SEGD[76] SEGD[75] SEGD[74] SEGD[73] SEGD[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64]
4565.34 4690.74 4816.14 4941.54 5066.94 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5265 5132.31 4998.31 4864.31 4730.31 4596.31 4462.31 4328.31 4194.31 4060.31 3926.31 3792.31 3658.31 3524.31 3390.31
-1755 -1755 -1755 -1755 -1755 -1274.3 -1148.9 -1023.5 -898.1 -772.7 -647.3 -521.9 -396.5 -271.1 -145.7 -20.3 105.1 230.5 355.9 481.3 606.7 732.1 857.5 982.9 1116.9 1250.9 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 Version:V1.1
October 31, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Pin No. Name

Pin No.
Name
HE84G770
HE80004H SERIES
Y Coordinate
X Coordinate
Y Coordinate
X Coordinate
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
LVL4 LVL3 LVL2 LVL1 LGS1 LVREG LVR12 GND:G VO DAO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P SXO SXI VX OLFR OCCK VDD:P PRTD[7] PRTD[6] PRTD[5] PRTD[4] PRTD[3] PRTD[2] PRTD[1] PRTD[0] GND_PWM:G PWM IRO CS3_N CS2_N VDD_RAM:P PRTC[7] PRTC[6] PRTC[5]
-3181.82 -3056.42 -2931.02 -2805.62 -2680.22 -2554.82 -2429.42 -2294.22 -2121.92 -1949.62 -1844.62 -1739.62 -1634.62 -1529.37 -1421.82 -1316.82 -1211.57 -1106.57 -1001.57 -896.57 -791.57 -686.57 -581.57 -476.57 -371.57 -266.57 -161.57 -56.56 48.44 153.44 258.44 365.44 488.39 595.39 700.64 805.89 911.49 1044.14 1169.54 1294.94
-1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 9
146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185
SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SGKY[43] SGKY[42] SGKY[41] SGKY[40] SGKY[39] SGKY[38] SGKY[37] SGKY[36] SGKY[35] SGKY[34] SGKY[33] SGKY[32] SGKY[31] SGKY[30] SGKY[29] SGKY[28] SGKY[27] SGKY[26] SGKY[25] SGKY[24]
3256.31 3122.31 2988.31 2854.31 2720.31 2586.31 2452.31 2318.31 2184.31 2050.31 1916.31 1782.31 1648.31 1514.31 1380.31 1246.31 1112.31 978.31 844.31 710.31 584.91 459.51 334.11 208.71 83.31 -42.09 -167.49 -292.89 -418.29 -543.69 -669.09 -794.49 -919.89 -1045.29 -1170.69 -1296.09 -1421.49 -1546.89 -1672.29 -1797.69
1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 Version:V1.1
October 31, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Pin No. Name

Pin No.
Name
HE84G770
HE80004H SERIES
Y Coordinate
X Coordinate
Y Coordinate
X Coordinate
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
PRTC[4] CMSG[32] CMSG[33] CMSG[34] CMSG[35] CMSG[36] CMSG[37] CMSG[38] CMSG[39] CMSG[40] CMSG[41] CMSG[42] CMSG[43] CMSG[44] CMSG[45] CMSG[46] CMSG[47] CMSG[48] CMSG[49] CMSG[50] CMSG[51] CMSG[52] CMSG[53] CMSG[54] CMSG[55]
1420.34 1555.74 1681.14 1806.54 1931.94 2057.34 2182.74 2308.14 2433.54 2558.94 2684.34 2809.74 2935.14 3060.54 3185.94 3311.34 3436.74 3562.14 3687.54 3812.94 3938.34 4063.74 4189.14 4314.54 4439.94
-1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755 -1755
186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209
PRT14[7] PRT14[6] PRT14[5] PRT14[4] PRT14[3] PRT14[2] PRT14[1] PRT14[0] PRT15[7] PRT15[6] PRT15[5] PRT15[4] PRT15[3] PRT15[2] PRT15[1] PRT15[0] PRT17[7] PRT17[6] PRT17[5] PRT17[4] PRT17[3] PRT17[2] PRT17[1] PRT17[0]
-1923.09 -2048.49 -2173.89 -2299.29 -2424.69 -2550.09 -2675.49 -2800.89 -2926.29 -3051.69 -3177.09 -3302.49 -3427.89 -3553.29 -3678.69 -3804.09 -3929.49 -4054.89 -4180.29 -4305.69 -4431.09 -4556.49 -4681.89 -4807.29
1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755 1755
October 31, 2003
10
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd

HE84G770
HE80004H SERIES
6. ROM Map Configurations
The chip has built-in 1M bytes internal ROM including 512K bytes program ROM and 512K bytes data ROM. In addition, address and data buses are provided to access External ROM. The MCU can access up to 4 MB Program ROM and up to 16 MB Data space through external buses. The SEG[79..72], SEG[71..44] pads are used as either data and address buses for external ROM or LCD segment driver pads depending on the mask option MO_EXMEM. When the external ROM mask option is selected, the MCU will retrieve the instructions and data from external ROM through the address and data buses and the SEG[79..44] will not be LCD segment signals. The bit 14 ~ 15 bit of 16-bit logical program address can be mapped to any one of 256 pages through mapping registers PSA1, PSA2, PSA3. As logical page 0 can not be moved and is always physical page 0, the PSA1 ~ PSA3 contain the physical page addresses of logical pages 1 ~ 3. Logical Address A9 A8 A7 A6 A9 A8 A7 A6
A15 A14 A13 A12 A11 A10 Page Addr. A13 A12 A11 A10 A[15..14] 00 01 10 11 Register Address PSA1 0x2C PSA2 0x2D PSA3 0x2E Type R/W R/W R/W
A5 A5
A4 A4
A3 A3
A2 A2
A1 A1
A0 A0
Logical Page Physical Page Address 0 0 1 PSA1 2 PSA2 3 PSA3
Physical Address 00 A[13..0] PSA1+A[13..0] PSA2+A[13..0] PSA3+A[13..0] Reset 0x01 0x02 0x03
A21 A21 A21
A20 A20 A20
A19 A19 A19
Bits Definition A18 A17 A18 A17 A18 A17
A16 A16 A16
A15 A15 A15
A14 A14 A14
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HE84G770
HE80004H SERIES
There are four configurations for external memory as determined by mask option MO_PMODE. For example, when option 0 is selected, 512 KB of internal ROM will occupy the address range from 0x000000 ~ 0x07FFFF of memory space, while CS1 controls external memory device whose address ranges from 0x200000 to 3FFFFF, etc. If the Option 1 is selected, the internal program/data ROM will be skipped and the external ROM will be active by CS0~2.
MO_ PMODE [1..0] Configuration 00 Option 0 01 Option 1 10 Option 2 11 Option 3
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HE84G770
HE80004H SERIES
Address 000000
Address 000000 080000 100000 200000
Option 0 Int. PROM (512KB) Unused CS0 CS1
Address 000000
Option 1
Address 000000 080000
CS0
100000 200000
Option 2 Int. PROM (512KB) Unused CS0 CS1
Option 3 CS0
100000 2FFFFF 300000 380000
CS1 Int. PROM (512KB) Unused
3FFFFF 400000
3FFFFF 400000
3FFFFF 400000 480000 600000
CS2
7FFFFF 800000 7FFFFF 800000
CS1
Int. DROM (512KB) Unused CS2
400000
CS2
7FFFFF 800000
7FFFFF 800000
CS3
FFFFFF FFFFFF
CS2
FFFFFF
CS3
FFFFFF
CS3
Legend:
Int. Program
Int. Data
Ext. Program
Ext. Data
Note: Option2 shall be selected when the internal "Data ROM" is used.
Intel NOR FLASH Ext. Bus Interface A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 MB EPROM A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS VCC A18 A17 A14 A13 A8 A9 A11 OE/VPP A10 CE Q7 Q6 Q5 Q4 Q3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A18 A17 A14 A13 A8 A9 A11 A10 CS0 Q7 Q6 Q5 Q4 Q3 VDD A16 A15 A14 A13 A12 A11 A9 A8 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A16 A15 A14 A13 A12 A11 A9 A8 WE RP VPP WP A18 A7 A6 A5 A4 A3 A2 A1 28F320-TSOP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A20 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 Q7 Q6 Q5 Q4 VDD 512KB x 8 SRAM A11 A9 A8 A13 WE A17 A15 VDD A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 LP62S4096-TSOP OE A10 CS1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS3 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A17 GND A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE GND CE A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 A20 A19 A10 DQ7 DQ6 DQ5 DQ4
SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79
CS1 CS0 WE OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0.1uF
M27C801 16 MB EPROM A19 A18 A8 A7 A6 A5 A4 A3 A2 A1 CS1 D0 Q1 Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 M27C160 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BY TE VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
A18 A7 A6 A5 A4 A3 A2 A1
DQ3 DQ2 DQ1 DQ0 OE CE A0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
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13
Version:V1.1
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HE84G770
HE80004H SERIES
7. External RAM/Flash Memory
The external memory devices can be mask ROM, static RAM, or NOR type FLASH memory. Most NOR type FLASH memory and RAM can be used as external storage for both program and data, so program can be downloaded to external memory devices for future execution. However, there are some limitations. When the data is to be written to external devices, the loader must reside in internal program space. In other words, the loader program must be in internal ROM. When download is completed, the program in the external memory can be run. The data written to external memory devices is through a command interface composed of AC, EXMC and EXMD registers for setting up the memory addresses, switching memory buses, generating read/write pulse, read/write memory contents, etc. When writing finishes, external memory can be switched back the external address and data bus for CPU to fetch data and instructions. Writing to address registers is through a common register AC. Writing to AC will write data to ACL, ACH, and then ACP in cyclic order. The sequence will be reset by an access to EXMD register. Therefore, it is advisable to make a dummy read to EXMD register before writing to AC, so that the first write will be made to ACL. AC Mode Description ACL R/W Address Counter Low for AC7 ~ AC0 ACH R/W Address Counter High for AC15 ~ AC8 ACP R/W Address Counter Page for AC23 ~ AC16 ACL: Lowest Significant Byte of Address Counter. ACH: 2nd Byte of Address Counter. ACP: Most Significant Byte of Address Counter. Register Mode EXMC W DNLD: Switch the bus to download bus. RD: Read pulse control. WR: Write pulse control. Description DNLD RD WR Reset Value "--------" "--------" "--------"
Reset Value "-----011"
After address setup, the data can be written to address device through EXMD register. Program must generate the required write pulse by firmware. The address counter AC will automatically increment with each read/write access. Register EXMD Type R/W D7 D6 D5 Description D4 D3 D2 D1 D0 Reset Value "--------"
The procedure for downloading data from I/O or any other sources, i.e. command mode ROM device is as follows: 1. Switch the external memory to download bus by setting the DNLD bit of EXMC register. 14 Version:V1.1
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2. 3. 4. 5.

HE84G770
HE80004H SERIES
6.
Make a dummy read to EXMD register to reset the AC pointer. Set up the address for transferring data by first writing to ACL, and then ACH and ACP with the first 3 writes to register. Start writing to addressed device by first writing 1 byte of data to EXMD register, clear WR bit of CMD register and set it again, the AC will increment with each write pulse. To read addressed device, clear RD bit of EXMC register, read EXMD register and set RD bit again. The AC will also increment with each read pulse. Read back for verification is optional. Please note that read back can also be made through external address and data bus when the bus is switched back to program bus. Switch back to normal bus for program execution and data access by clearing the DNLD bit of EXMC register.
Please note that NOR FLASH memory from different manufacturers such as Intel, AMD, SST, etc. requires various command sequence to set up. Programmer still needs to follow the respective specifications of the vendors.
8. LCD Display RAM Map
The gray-scale LCD driver can be configured to be a 16 gray-scale, 4 gray-scales or black and white display by mask option MO_GRAY_MODE. MO_GRAY_MODE[1..0] 00 01 10 11 Gray levels 16 4 2 (B/W) 2 (B/W)
For 4 gray-scale displays, 2-bit of RAM is required for each pixel and 4 bit for 16 gray-scale display, 1-bit for black and white display. For different LCD configuration, the LCD display RAM is arranged differently. The following figure shows one byte of RAM in different LCD configurations: 0F xx 0E xx 0D xx 0C xx 0B xx 0A xx 09 xx 08 xx 07 xx 06 xx 05 xx 04 xx 03 xx 02 xx 01 xx 00 xx
Black/White 4 Gray scales 16 Gray scales
Bit 7 Bit 6 Bit 5 Bit 4 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Bit 3 Bit 2 Bit 1 Bit 0 SEG3 SEG2 SEG1 SEG0 SEG1 SEG0 SEG0
The 16 Gray Scale register GRAY0 ~ GRAYF is the mapping register between the levels selected in RAM and the real gray scale. In other words, if the content of GRAY0 is 0x03, when value of a certain pixel is 0, the displayed effect will correspond to actual gray level 3. The 16 gray scale display use all 16 registers GRAY0 ~ GRAYF to select among 32 available gray levels to correspond to level 0 ~ 15, while October 31, 2003 15 Version:V1.1
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HE84G770
HE80004H SERIES
4 gray scale display utilizes registers GRAY0 ~ GRAY3 to select among 32 gray levels to correspond to level 0 ~ 3. Thus user can pick the gray levels which give the best and most linear effect. 16 Gray-scale registers share a common register address GRAY16. When writing is made to the register, it will step down to next register in order. The writing sequence can be reset by clearing bit 5 of LCDC register. GRAY16 Seq. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bit4 Bit3 Field Bit2
GRAY0 GRAY1 GRAY2 GRAY3 GRAY4 GRAY5 GRAY6 GRAY7 GRAY8 GRAY9 GRAYA GRAYB GRAYC GRAYD GRAYE GRAYF
Bit1
Bit0
Reset
0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E
9. LCD driver configurations
There are 4 LCD configurations selectable by mask option MO_COM[1:0] for this chip. The function of CMSG[79..32] in each configuration is listed in the following table. MO_COM[1:0] 00 01 10 11 Configuration COM x SEG 32 x 128 48 x 112 64 x 96 80 x 80 CMSG[79..64] Function SEG[80..95] SEG[80..95] SEG[80..95] COM[79..64] CMSG[63..48] Function SEG[96..111] SEG[96..111] COM[63..48] COM[63..48] CMSG[47..32] Function SEG[112..127] COM[47..32] COM[47..32] COM[47..32]
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32X128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80
64X96 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80
80X80 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79
HE84G770
HE80004H SERIES
COMXSEG CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 CMSG64 CMSG65 CMSG66 CMSG67 CMSG68 CMSG69 CMSG70 CMSG71 CMSG72 CMSG73 CMSG74 CMSG75 CMSG76 CMSG77 CMSG78 CMSG79
48X112 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80
Since there are four LCD driver configurations available for selection by mask option, the RAM map of LCD drivers is listed below for all configurations. Any unused RAM as marked with `*' sign can be used as general purposed RAM by application programs.
9.1. 16 Gray Scale LCD Display RAM Map
32x128
Page
48x112 0 F
S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00
64x96 0 F
S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 * * *
80x80 0 F
S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00
F 00 10 20 30 40 50 60 70 80 90 A0 B0 C0
S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00
0 COM0
1
COM1
COM2 COM3
October 31, 2003
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32x128
Page
0 F
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
48x112
S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96
F D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 00 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30
S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96
S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * * * * * * * * * * * * * * *
S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 *
COM4
COM5
2
COM6
COM7
COM8
COM9
3
COM10
COM11
COM12
COM13
4
COM14
COM15
5
COM16
October 31, 2003
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32x128
Page
0 F
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
48x112
S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64
F 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0
S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64
S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * * * * * * * * * * * * * *
S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64
COM17
COM18
COM19
COM20
COM21
6
COM22
COM23
COM24
COM25
7
COM26
COM27
8
COM28
COM29 COM30
October 31, 2003
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Version:V1.1
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32x128
Page
0 F
*
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
48x112
S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32
F B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10
S127 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 S127 ~ S96 *
* S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 * * * * * * * * * * * *
* S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32
COM31
COM32
COM33
9
COM34
COM35
COM36
COM37
A
COM38
COM39
COM40
COM41
B
COM42
COM43 COM44
C
October 31, 2003
20
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
32x128
Page
0 F
0 F
64x96
0
F
*
80x80
HE84G770
HE80004H SERIES
0
S80 ~ S64
48x112
S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * S112 ~ S96 S31 ~ S00 S63 ~ S32 S95 ~ S64 * * S112 ~ S96
F 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80
S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00
* S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64
COM45
COM46
COM47
COM48
COM49
D
COM50
COM51
COM52
COM53
E
COM54
COM55
F
COM56
COM57 COM58
October 31, 2003
21
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
32x128
Page
0 F
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
48x112
F 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 * S31 ~ S00 S63 ~ S32 S95 ~ S64 S31 ~ S00 S63 ~ S32 S95 ~ S64 * * * * * * *
S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 S80 ~ S64 * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64
COM59
COM60
COM61
10
COM62
COM63
COM64
COM65
11
COM66
COM67
COM68
COM69
12
COM70
COM71
October 31, 2003
22
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
32x128
Page
0 F
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
48x112
F 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * S80 ~ S64 S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S31 ~ S00 S63 ~ S32 * * S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64 S80 ~ S64
COM72
COM73
13
COM74
COM75
COM76
COM77
14
COM78
COM79
9.2. 4 Gray Scale LCD Display RAM Map
Page
32x128 F 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 * * * * * * * *
48x112 0 F
S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 * * * * * * * *
64x96 0 F
S63 ~ S00
S96 ~ S64
80x80 0 F
S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 *
S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64
0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
1
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
October 31, 2003
23
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Page
0 F
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
32x128 F 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60
S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 S63 ~ S00 S127 ~ S64 * * * * * * * * * * * * * * * * * * * * * * * * * * * *
48x112
S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 * * * * * * * * * * * * * * * * * * * * * * * * * * *
S63 ~ S00
S96 ~ S64
S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00
S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
2
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
3
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
4
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
5
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
S96 ~ S64
S63 ~ S00
October 31, 2003
24
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Page
0 F
* * * * * * * * * * * * *
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
32x128 F 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0
48x112
S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 S63 ~ S00 S112~ S64 * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
S96 ~ S64
* S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 *
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
6
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
7
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
8
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
S63 ~ S00
S96 ~ S64
S80~ S64
October 31, 2003
25
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Page
0 F
0 F
64x96
0
F
80x80
HE84G770
HE80004H SERIES
0
32x128 F E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
48x112
S63 ~ S00 *
S96 ~ S64
S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 * S63 ~ S00 *
S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64 S80~ S64
COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79
9
*
S80~ S64
A
9.3. Black and White LCD Display RAM Map
Page
32x128 F 0
S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 * * * * * * * * * * * * * *
48x112 F
S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00
64x96 0
* * * * * * * * * * * * * *
80x80 0 F
* * * * * * * * * * * * * * S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00
F
S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00
0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13
0
00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0
October 31, 2003
26
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Page
0 F
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
0
F
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
64x96
0
F
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
80x80
HE84G770
HE80004H SERIES
0
32x128 F E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 00 10 20 30 40
S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 S127 ~ S00 *
48x112
S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 S111 ~ S00 *
S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 S95 ~ S00 *
S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00
1
2
3
4
COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68
October 31, 2003
27
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
Page
0 F
0
F
64x96
0
F
* * * * * * * * * * *
80x80
HE84G770
HE80004H SERIES
0
32x128 F 50 60 70 80 90 A0 B0 C0 D0 E0 F0
48x112
S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00 S79 ~ S00
COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79
October 31, 2003
28
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd

HE84G770
HE80004H SERIES
10. LCD Power Supply
The built-in LCD power supply is equipped with input voltage regulator, voltage multiplier and bias voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The input voltage is regulated to LVREG using the internally generated LVAG as reference voltage. LVREG can be adjusted by resistors between LGS1 and LVREG. LVREG adjustment guideline: First, the level of LVREG must be at least 0.4 volt lower than VDD at all time, even at the end of battery life, for the regulator to function properly. For example, if the VDD is expected to drop to 2.2 volts when battery is low, then the level of LVREG can only be set at 1.8 volts max. With this constraint, it is advisable to set the level of LVREG as high as possible and use less charge pump stages to save power. For example, to pump the 2 volts to 12 volts requires 6 charge pump stages; to pump the 2.4 volts to 12 volts requires only 5 charge pump stages which consumes less power. So it is recommended not to adjust the LVREG to an unnecessary low level. Voltage charge pump: The LVREG is then multiplied by 3, 4, 5, or 6 times, depending on external capacitors configurations as shown below, to generate LVL5. Please note that LVL5 must be lower than 12 volts to prevent chip from break-down. The capacitance of capacitors connected to LVL1~5 shall be increased in an appropriate amount based on the LCD panel size. For small size LCD panel, the 10uF capacitors are enough, but 22uF capacitors may be necessary for large LCD size application.
x3 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A 1uF 1uF LCAP2A LCAP1A 1uF 1uF 1uF x4 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A 1uF 1uF 1uF 1uF x5 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A 1uF 1uF 1uF 1uF 1uF x6 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A
The internal reference voltage has built-in temperature compensation to make up the reference voltage deviation due to the temperature variation. Four temperature coefficients are available for selection by mask option MO_TC. It's used to compensate the LCD display feature in the range of room temperature to low temperature. User shall set the MO_TC value based on the LCD feature and operation environment. If the MO_TC is set to "11", the LCD power voltage will have 0.33% decrease when the temperature increases one degree.
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MO_TC 00 01 10 11 Temp. Coef. -0.0 %/C -0.16 %/C -0.22 %/C -0.33 %/C
HE84G770
HE80004H SERIES
Heavy LCD load: The bias voltages LVL1 ~ LVL5 for LCD driver are generated from internal bias network and buffered with active drive to provide greater bias driving strength. Usually larger LCD panel needs more power to drive. Four driving capabilities, which can be selected by mask option, are provided to suit the needs of application. Please note that high driving capability will cause the power consumption to be increased. MO_LOAD Driving Current 00 Low 01 Medium 10 Medium high 11 High External LCD power supply: If the maximal driving option is still inadequate for applications, user may choose to use the external LCD power supply. In that case, there are still several options: First, use the internal regulator and charge pump circuit to generate the high voltage, but use external bias network to generate and supply the bias voltage level LVL1 ~ LVL5. In this case, the buffered active drive for internal bias needs to be turned off to avoid confliction with external bias circuit and DC current drain. The second option is to turn off internal charge pump circuit, and use external DC-to-DC circuit to generate high voltage and use internal bias network and buffer active drive to generate bias voltages. The third option is to turn off internal regulator, charge pump circuit, and bias buffer circuit and use external circuit to generate the high voltage and bias voltage. The individual circuit can be turned on or off by the appropriate bit in LCDC and LCDPS registers and MO_PUMPE mask option. Configuration External charge-pump/External bias circuit External charge-pump/Internal bias circuit Internal charge-pump/ External bias circuit Internal charge-pump/Internal bias circuit
Address NAME 0FH LCDC 24H LCDPS
MO_PUMPE 0 0 1 1
BUFE 0 1 0 1
Internal Internal Charge pump Bias Buffer
-
-
CLR_GP -
-
Field BLANK Reserved POWDN PAcc
LCDE BUFE
Mode W R/W
RESET --1x xx10 ---- -100
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Value 0 POWDN 1 0 PAcc 1 0 BUFE 1 0 CLR_GP 1 0 BLANK 1 LCDE 0 1 Field

HE84G770
HE80004H SERIES
Function LCD power system enabled. LCD power system disabled. Internal Charge-pump doesn't accelerate to charge the capacitor. Internal Charge-pump accelerates to charge the capacitor. Disable internal bias network buffer Enable internal bias network buffer Reset GRAY palette register pointer by write `0' to CLR_P bit. No effect on GRAY palette register pointer normal display LCD display blanked. The COM signals of LCD driver output inactive levels (LVL4 and LVL1) while SEG signals output normal display patterns. LCD driver disabled, LCD driver has no output signal and LVL1 ~ LVL5 is pulled up to VDD LCD driver master control enabled
Bias Setting: Different duties require different bias settings. There is some theoretical correspondence between the Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel connected to it to determine the final setting. The theoretic relationship between the duty and bias setting is as the following table: However, the actual bias setting should be determined based on the best visual effect given when the target LCD panel is connected. Duty Cycle 32 duty 48 duty 64 duty 80 duty Normal Bias Setting 1/7 1/8 1/9 1/10
The bias setting is made by mask option MO_LBSR[1..0]. MO_LBSR[1..0] 00 01 10 11 Bias Setting 1/7 1/8 1/9 1/10
Please note that LCD driver must be turned off before the IC goes into sleep mode. That means user must clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep mode. Large current might happen if the procedure is not followed. Please note that LCD driver uses slow clock as clock source. The LCD display will not display normally if it works in Fast clock only mode because the LCD refresh action is too fast. The LCD power system shall be enabled by set POWDN to `1' before the LCD display is enabled. In order to accelerate the capacitor charging, the "PAcc" bit shall be set when the LCD power system is initialized and then "PAcc" can be cleared when the LCD power system is stable.
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11. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to choose from. The system designer can select oscillator types based on the cost target, timing accuracy requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components should be placed as close to the pins as possible. The type of oscillator used is selected by mask option MO_FXTAL. MO_FXTAL Fast clock type 0 RC Oscillator. 1 Crystal Oscillator.
FXI FXI
FXO
FXO
Crystal Osc.
RC Osc.
The RC oscillator has a built-in capacitor. An external resistor is needed to connect from FXI to GND to determine the oscillation frequency. The capacitance of internal RC oscillator is selected by mask option MO_RCAP[2..0]. MO_RCAP[2:0] 000 001 010 011 100 101 110 111 Internal RC Cap. (pF) 2 4 7 14 20 40 50 60
The following table shows the combinations of R and C, and the resulting frequency. Please note that oscillation frequency in the table only represents oscillation frequencies of certain samples. The actual oscillation frequency may vary up to 15% from lot to lot due to process parameter variations. User must take this into consideration when using this chip in applications.
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Ring Oscillator Frequency Table
R (K) C
HE84G770
HE80004H SERIES
40 0.8 1.2 2.3
20 1.5 2.2 4.0
14 2.0 2.8 5.1
7 3.0 4.4 7.5
4 4.0 5.6 -
2 5.0 MHz 7.0 MHz - MHz
30.20 19.92 9.98
Two types of oscillator, crystal and RC, can be used as slow clock selectable by mask option MO_SXTAL. If used time keeping function or other applications that required the accurate timing, crystal oscillator is recommended. If the timing accuracy is not important, then RC type oscillator can be used to reduce cost. MO_SXTAL 0 1
SXI SXI
Slow clock type R/C oscillator Crystal oscillator
SXO Crystal Osc.
SXO
RC Osc.
With two clock sources available, the system can switch among operation modes of Normal, Slow, Idle, and Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of application such as high speed or low power, etc. OP1 Field Mode Reset OP2 Field Mode Reset Bit 7 DRDY R/W 1 Bit 7 IDLE R/W 0 Bit 6 STOP R/W 0 Bit 6 PNWK R Bit 5 SLOW R/W 0 Bit 5 TCWK R Bit 4 INTE R/W 0 Bit 4 TBE R/W 0 Bit 3 T2E R/W 0 Bit 3 R/W Bit 2 T1E R/W 0 Bit 1 Z R/W Bit 0 C R/W Bit 0 R/W -
Bit 2 Bit 1 TBS[3..0] R/W R/W -
If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from slow clock while the other blocks will operate with the fast clock.
12. General Purpose I/O
There are two dedicated general purpose I/O ports, PRTC[7..4] and PRTD, while the PRT14, PRT15 and PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of non-
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HE80004H SERIES
tri-state output structure. The output has weak sourcing (50 A) and stronger sinking (1 mA) capability and each can be configured as push-pull or open-drain output structure individually by mask option. When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a floating pad could cause more power consumption since the noise could interfere with the circuit and cause the input to toggle. A `1' needs to be written to port first before reading the input data from the I/O pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path between pull-up and external circuit. The input port has built-in Schmidt trigger to prevent it from chattering. Hysteresis level of Schmidt trigger is 1/3 VDD.
VDD VDD
DOUT
Q LATCH Q' MO_?PP
PAD
DIN SCHMIDT Trigger input
As pads of PRT14, PRT15 and PRT17 are shared with LCD segment driver, the function of the pad is determined by mask options. Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to LCD display setting and pin assignment features. MO_LIO?[...] MO_?PP[...] I/O Port LCD Pin 0 0 Open-drain output -0 1 Push-pull output -1 0 -xx 1 1 -LCD Display --: Function not available. xx: Displayable, but may have abnormal leakage current, do not use.
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13. Key Scan Circuit
The built-in 4x20 hardware keyboard scan circuit helps to reduce the pin counts where application requires large key matrix and high LCD pixel count as well as the firmware effort. As key-scan pins are shared with LCD segment and PRTC4 ~ PRTC7 pins, it is advisable to put resistors between segment pins and key matrix to avoid shorting the segment pins when two or more keys in the same row are pressed simultaneously. Two key can be detected simultaneously and the first detected key code is stored in KEY0 register and the second in KEY1 register respectively. The key code for each key location is listed in the following table. Key Loc SCNO0 SCNO1 SCNO2 SCNO3 SCNO4 SCNO5 SCNO6 SCNO7 SCNO8 SCNO9 SCNO10 SCNO11 SCNO12 SCNO13 SCNO14 SCNO15 SCNO16 SCNO17 SCNO18 SCNO19 SCNI0 SCNI1 SCNI2 0x80 0xA0 0xC0 0x81 0xA1 0xC1 0x82 0xA2 0xC2 0x83 0xA3 0xC3 0x84 0xA4 0xC4 0x85 0xA5 0xC5 0x86 0xA6 0xC6 0x87 0xA7 0xC7 0x88 0xA8 0xC8 0x89 0xA9 0xC9 0x8A 0xAA 0xCA 0x8B 0xAB 0xCB 0x8C 0xAC 0xCC 0x8D 0xAD 0xCD 0x8E 0xAE 0xCE 0x8F 0xAF 0xCF 0x90 0xB0 0xD0 0x91 0xB1 0xD1 0x92 0xB2 0xD2 0x93 0xB3 0xD3 SCNI3 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3
KEY0 0x22 KEY1 0x23
BIT7 R BIT7 -
BIT6 BIT5 Row Index BIT6 BIT5 Row Index
BIT4
BIT3
BIT2 BIT1 Column Index BIT2 BIT1 Column Index
BIT0
BIT4
BIT3
BIT0
The bit 7 of KEY0 and KEY1 is repeat indicator when the same key is scanned for the second time, the R bit will be cleared to indicate the key is not released yet.
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The key-scan function can be turned on/off by mask option MO_LCDKEY. MO_LCDKEY SGKY[43..24] Function 0 as SEG only 1 as SEG as well as KEY_SCAN The pulse width of key-scan signal can be selected by mask options MO_SNCK[1:0]. MO_SNCK[1..0] 00 01 10 11 Key Scan Pulse Width 0.5 SCK 1.0 SCK 1.5 SCK 2.0 SCK
HE84G770
HE80004H SERIES
The strength of key-scan signal can also be selected by mask options MO_SCDRV[1:0]. MO_SCDRV[1..0] 00 01 10 11 Key Scan Signal Strength weakest weak strong strongest
SCNO0 SCNO1 SCNO2 SCNO3 SCNO17 SCNO18 SCNO19 SCNI0 SCNI1 SCNI2 SCNI3
SGKY 24 SGKY 25 SGKY 26 SGKY 27 : SGKY 41 SGKY 42 SGKY 43 47K PRTC4 PRTC5 PRTC6 PRTC7
47K 47K 47K ....
47K
47K
47K
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HE80004H SERIES
14. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt will be generated when the counter underflows - counts down to FFFFH. And the counter will be automatically reloaded with the value of T1H and T1L. The clock source of Timer1 is derived from slow clock "SCK" at dual clock or slow clock only mode. And it comes from the fast clock "FCK" at fast clock only mode. Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be set before enabling Timer1.
Auto reload when Timer1 is underflow
The contents of T1H and T1L are almost loaded into Timer1 immediately when Timer1 is enabled after reset.
T1H
T1L
< Timer1 Counter > Decreases 1
No
Count To 0xFFFFh
Yes Timer1 Interrupt Request T1_INT
The Timer1 related control registers are list as below: Register Address Field Bit position Mode IER T1L T1H OP1 0x02 0x03 0x04 0x09 TC1_IER T1L[7:0] T1H[7:0] TC1E 2 7~0 7~0 2
Description 0: TC1 interrupt is disabled. (default) R/W 1: TC1 interrupt is enabled. W Low byte of TC1 pre-load value W High byte of TC1 pre-load value 0: TC1 is disabled. (default) R/W 1: TC1 is enabled.
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HE80004H SERIES
15. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock "Fsys"/1.5. The system clock "Fsys" varies depending on the operation modes of the MCU. The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded with the value of T2H and T2L. Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value should be set before enabling Timer2. The Timer2 related control registers are list as below: Register IER T2L T2H OP1 Address 0x02 0x05 0x06 0x09 Field TC2_IER T2L[7:0] T2H[7:0] TC2E Bit Position 1 7~0 7~0 3 Mode Description 0: TC2 interrupt is disabled. (default) R/W 1: TC2 interrupt is enabled. W Low byte of TC2 pre-load value W High byte of TC2 pre-load value 0: TC2 is disabled. (default) R/W 1: TC2 is enabled.
The contents of T2H and T2L are almost loaded into Timer2 immediately when Timer2 is enabled after reset.
T2H
T2L
Auto reload when Timer2 is underflow
< Timer2 Counter > Decreases 1
No
Count To 0xFFFFh
Timer2 Interrupt Request
Yes
T2_INT
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HE80004H SERIES
16. Time Base
The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit controls enable or disable of the circuit. OP2 Field Mode Reset Bit 7 IDLE R/W 0 Bit 6 PNWK R Bit 5 TCWK R Bit 4 TBE R/W 0 Bit 3 R/W Bit 2 Bit 1 TBS[3..0] R/W R/W Bit 0 R/W -
TBE Function 0 Disable Time Base 1 Enable Time Base For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table. TBS[3..0] Interrupt Frequency 0000 16.384 KHz 0001 8.192 KHz 0010 4.096 KHz 0011 2.048 KHz 0100 1.024 KHz 0101 512 Hz 0110 256 Hz 0111 128 Hz 1000 64 Hz 1001 32 Hz 1010 16 Hz 1011 8 Hz 1100 4 Hz 1101 2 Hz 1110 1 Hz 1111 0.5 Hz
17. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically and prevents system dead lock caused by abnormal hardware activities or program execution. The WDT needs to be enabled in Mask Option. MO_WDTE 0 1 Function WDT disable WDT enable
Using the WDT function, the "CLRWDT" instruction needs to be executed in every possible program path when the program runs normally in order to clears the WDT counter before it overflows, so that the
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HE84G770
HE80004H SERIES
program can operate normally. When abnormal conditions happen to cause the MCU to divert from normal path, the WDT counter will not be cleared and reset signal will be generated to reset the system. The WDT clock source is the same as TC1 (Timer1 clock), and the WDT reset signal is generated when the counter had counted 32768 clock. The WDT can function in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock has stopped).
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HE80004H SERIES
18. Voice Output
There are 7 or 8 bits DAC/PWM voice output available for user. The 7 bits DAC/PWM output format and configuration are the same as the previous IC of HE80004H series. The 8 bits DAC/PWM format and configuration are new designed and controlled by the VOC and PWMC registers. The selection of 7/8 bits DAC/PWM output is by mask option MO_8BVOC. MO_8BVOC 0 1 Function 7-bit DAC/PWM output 8-bit DAC/PWM output
8-Bit DAC/PWM Output: The Digital-to-Analog converter converts the 8-bit unsigned speech data which is written into PWMC data register to proportional current output.
PWMC Field
address 0x0E
Reset --
bit 7 DA7
bit 6 DA6
bit 5 DA5
bit 4 DA4
bit 3 DA3
bit 2 DA2
bit 1 DA1
bit 0 DA0
There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by VOC register when it is enabled. The VO output is primarily intended for speech generation, although it is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to function as an Analog-to-Digital Converter as required in applications such as speech recording, speech recognition or sensor interfaces.
OPO OP + 1 PWMC[DATA] DAC 0 OPIP OPIN DAO VO R VOC[DAC] VOC[OP]
The DAC is enabled by DAC bit of VOC register. When DAC is enabled, the DAC output path can be selected to output to DAO or VO pin by OP bit of VOC register.
VOC Field Reset
address 0x13
Bit 7 -
Bit 6 Bit 5 Bit 4 PWM O/P driver 0 0 0
Bit 3 PWME 0
Bit 2 PWM 0
Bit 1 DAC 0
Bit 0 OP 0
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Bit

HE84G770
HE80004H SERIES
Value 1 VOC[3] PWME 0 1 VOC[2] PWM 0 1 VOC[1] DAC 0 1 VOC[0] OP 0
Name
Function description PWM Output Driver Enable PWM Output Driver Disable PWM Module Enable PWM Module Disable Digital-to-Analog Converter Enable Digital-to-Analog Converter Disable DAC output to DAO pin DAC output to VO pin
The pulse-width modulator (PWM) converts 8-bit unsigned speech data which is written into PWMC data register to proportional duty cycle of PWM output. PWM module shares the same digital input register PWMC with Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is enabled, it generates signal with duty ratio in proportion to the value of PWMC register.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
The PWM bit of VOC controls the enable/disable of the PWM circuit and output driver. When PWM bit of VOC is `0', PWME bit and output drivers are both cleared. To use PWM as voice output, PWM bit has to be set to `1' first, then set PWME bit and enable output driver by setting the driver number. If PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear. The Fast Clock is gated through PWME bit of VOC register to provide the clock source of PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct PWM signal in Slow clock only mode. When the program enters into sleep mode or idle mode, it will automatically turn off all voice outputs by clearing VOC[6:0] to "0000000". To activate voice output again when returning to normal mode, the VOC register needs to be set again. The PWM output volume can be adjusted by command register VOC[6..4]. The bit 6 and 5 control 2 time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the internal drivers, the sound level of PWM output can be turned up and down. Please note that this October 31, 2003 42 Version:V1.1
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adjustment apply only to PWM, but not DA output.
HE84G770
HE80004H SERIES
PWM output driver selection VOC[6..4] Number of Driver 000 off 001 1 010 2 011 3 100 2 101 3 110 4 111 5
7-Bit DAC/PWM Output: The 7-bit DAC/PWM voice generator is another scenario and the definitions of PWMC and VOC registers are different from the 8-bit DAC/PWM format. These registers are different from the 8-bit architecture and described as following.
The 7-bit voice output is controlled by PWMC and VOC register, and the PWMC is a command/data register which is determined by PWMC[7] bit. The VOC is a three bit voice control register in the 7-bit mode. VOC address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Field 0x13 PWM Reset 0 PWM: `1' PWM output enabled; `0' PWM output disabled. DAC: `1' DAC enabled; `0' DAC disabled. OP: `1' DAC uses DAO pin as output pin; `0' DAC uses VO pin as output pin. PWMC register DA & PWM Data Control Bit 7 0 1 Bit 6 Bit 4 Bit 3 Bit 2 DA and PWM output value PWM O/P driver Reserved Bit 5 Bit 1 DAC 0 Bit 0 OP 0
Bit 1
Bit 0 PWME
When users write data into the PWMC register, the PWMC[7] bit will determines the data written into PWM command register or 7-bit data register and the data register is also sent to the DA converter shown as the below diagram. The definitions of "PWME" bit and "PWM O/P driver" bits are the same as VOC register definition of 8-bit output mode.
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HE80004H SERIES
7-bit Voice Output Architecture
VOC[2]
#reset
PWM Command Register PWMC_REG[6..4] PWM Driver #reset PWM PWM_GND
PWMC[6..0] PWMC[7] Write_Strobe
clk
PWMC_ REG[0]
clk
Fast_clock
7-bit PWM Data Register
PWMO_REG[6..0]
DAC
VO/ DAO
clk
VOC[1] VOC[0]
The fast clock is used to provide as PWM driver time base, and user shall set the PWMC[7]='1' and VOC[2]='1' to enable the PWM output. When the system enters into sleep or idle mode, it will automatically turn off the voice device by clearing VOC[2:0] to "000". In order to activate voice output again when the system returns and enter into normal mode, the related bits of VOC register need to be set again.
PWM Data=0x40h
Data=0x10h
Data=0x70h subframe
When the DAC is used as sound generator, the bias & filter circuit is used for bias voltage setting and waveform filter regulation and the DAC is output to the VO (Voice Output) pin and please see application notes for detailed calculation example and application. The driving capability of DAC is shown below. Condition VDD=3V;VO=0~2V;Data=7Fh 44 Min. 2.5 Typ. 3 Max. Unit mA Version:V1.1
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HE80004H SERIES
VDD
CPU
VO(DAO)
bias & filter circuit
SPEAKER
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19. Low Voltage Detection/Reset
The low voltage detection is used to detect low battery or low power condition. There are 4 options on the detection level selectable by mask option MO_DLVL. The low voltage detection circuit can be turned off by clearing LVDE bit, and the status of supply power can be read out at bit LVDO of LVDC register (extension register 0x17h). MO_DLVL 00 01 10 11 Detection voltage 2.4 volts 2.6 volts 2.8 volts 3.0 volts
LVDC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Field LVDO LVDE Mode R W Reset 0 LVDO: `0' Battery level low; `1' Battery level high LVDE: `0' Disable voltage Detection, `1' Enable voltage Detection Low voltage reset circuit prevents the CPU from operating below its physical limit. When the supply voltage drops below VDET (2.2Volt), the CPU will be held in reset state until the supply voltage rises to VRLS. Then CPU will be released from reset state. VRLS will be higher than VDET by 5% to provide hysteresis and prevent CPU from bouncing back and forth between reset and operating state. The low voltage reset function can be enabled or disabled by mask option MO_LVRE. MO_LVRE Function 0 Disable LVR 1 Enable LVR The voltage detection circuit is temperature compensated to prevent the detection voltage from drifting with temperature variation.
Vrst
Vdet
Vrls
VDD
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HE80004H SERIES
20. Infrared output
To achieve an IR output with programmable frequency and duty cycle, two 7-bit registers are employed here. The IRH register represents the period (on FCK clock number) of output high, while IRL register represents the period of output low. With this mechanism, the output IR frequency is equal to FCK/(IRH+IRL), and the high duty cycle ratio is equal to IRH/(IRH+IRL). To make the IRO as output pin alone, either IRH or IRL can be set as 0. When IRH is 0, the IRO output is a DC low. On the contrary, if IRL is 0, the output is a DC high. Special care in hardware implementation is also taken according to the MO_IRO (mask option to determine the default state of the IRO) to avoid glitch when PWM output is disabled.
IRO
IRO IRH IRL
1 0
Toggle signal
MUX
Compare
IR generator
IRO
IRH=0?
Fck
CK
7-bit
R reset
To avoid unexpected IR output, users should firstly load the content of IRH and IRL before turn on IR by set IROE bits to `1'. The access of all the registers of IR is through the extension register. They are list as below: Extension register Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x15h IRL IROE IR PWM LOW DURATION 0x16h IRH IR PWM HIGH DURATION IROE: `0' IR is disabled (default); `1' IR is enabled. Bit0 Mode R/W W Reset value 0xxx xxxx -xxx xxxx
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MO_IRO
IRL=0?
Counter+1
D Counter Q
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HE84G770
HE80004H SERIES
21.
Universal Asynchronous Receiver/Transmitter
Full duplex Asynchronous communication Programmable transmission rate with internal baud rate generator with selectable bit rates Double buffered Transmitter and Receiver. Programmable Data length (from 5 to 8 bits) Programmable stop bits (1, 1.5 or 2-stop bit) generation and detection Programmable parity type (odd, even or no parity) Error (parity, overrun and framing errors) detection Fully prioritized interrupt system control Line break generation and detection.
The UART (Universal Asynchronous Receiver/Transmitter) interface provides serial communication capabilities with other devices such as PC. Features include:
Example - 8-bit UART Frame Format: (1 Start Bit, 8 Data Bits, 1 Parity Bit, 1 Stop Bit)
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HE84G770
HE80004H SERIES
Trans Hoding Reg
Trans Shift Reg
SOUT
TRANSMIT MACHINE
EX_PT[7:0]
Data Bus Buffer
Line Control Reg
"Transmitter
control signal"
TRANSMITTER TIMING AND CONTROL
"Transmitter status" ADS_N XRD_N XWR_N MCLK
MCU I/F CTRL LOGIC
Div Latch (MS)
BAUD-RATE GENERATOR
Div Latch (LS)
BrgClk
Line Status Reg
"Receive status"
control signal"
"Receiver
RECEIVE TIMING AND CONTROL
RESET
Interrupt Id Reg
Rec Buffer Reg
RECEIVE MACHINE
Interrupt En Reg
Interrupt Arbitrator
INTR
Rec Shift Reg
SIN
21.1. Interface Registers
Addressable extension register used to interface with MCU
Address 00H 01H 02H 03H 04H 05H 06H Name RBR THR IEIR LCR BRL BRH LSR Function UART RECEIVER BUFFER UART TRANSMITTER HOLDING REGISTER RLSI THRI RBRI 0 ID2 ID1 SB SP EPS PEN STB WLS1 UART LSB of Baud Rate Register UART MSB of Baud Rate Register TEMT THRE BI FE PE OE Mode R R/W R/W R/W R/W R/W R RESET 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000
0 BRGE
ID0 WLS0
0
DR
IEIR: Interrupt enable/disable identification register. LCR: Line control register. LSR: Line status register.
21.2.Baud Rate Configuration Register
The BRH and BRL registers hold the upper and lower bytes of 16 bit baud rate divisor and which are readable/writable. The baud rate of UART is calculated as following:
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BAUD _ RATE _ DIVISOR =
HE84G770
HE80004H SERIES
FCK , (FCK: fast clock of system) 16 * BAUD _ RATE
The contents of BRH and BRL are calculated by the following two formulas: BRL = BAUD _ RATE _ DIVISOR % 256 BRH = ( BAUD _ RATE _ DIVISOR - BRL) / 256
The "%" symbol is the modulus operation (reminder of division). For example, if the FCK is 1.8432M Hz and the desired baud rate is 2400 baud, then
BAUD _ RATE _ DIVISOR = 1843200 = 48 16 * 2400
The BRL register shall be set to 0x30 and BRH set to 0x00. The setting of baud_rate_divisor is not updated until the BRH register is written. Thus user is strongly recommended to write BRL first, then BRH. In order to obtain good communication quality, the same time base shall be used in the both sides of transmitting and receiving. The following table shows the most common baud rate setting used in the PC UART communication.
BRL and BRH: Baud Rate Control Registers FCK(Hz) Baud Rate (bps) Divisor BRL BRH 1.8432M 50 2304 0x00 0x09 1.8432M 300 384 0x80 0x01 1.8432M 1200 96 0x60 0x00 1.8432M 2400 48 0x30 0x00 1.8432M 4800 24 0x18 0x00 1.8432M 9600 12 0x0C 0x00 1.8432M 19200 6 0x06 0x00 1.8432M 38400 3 0x03 0x00 1.8432M 57600 2 0x02 0x00 1.8432M 115200 1 0x01 0x00
21.3. Interrupt Enable, Identification Register
This high nibble of IEIR register allows to enable/disable interrupt generation by the UART, the low nibble ID[2..0] of IEIR register is used to identify the source of interrupts.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value 0 RLSI THRI RBRI 0 ID2 ID1 ID0 "0000_0000" R/W R/W R/W R R R RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disable), related to ID[1] bit. THRI: Transmitter Hold Register Interrupt (1 = Enable, 0 = Disable), related to ID[0] bit. RLSI: Receiver Line Status Interrupt (1 = Enable, 0 = Disable), related to ID[2] bit. Address 0x02h Name IEIR
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The following table shows the related interrupt sources, user can read the ID[2:0] to retrieve what is the current highest priority of pending interrupts. The ID[2:0] bits will be cleared when user read the related registers. For example, when an interrupt happened and the content of ID[2:0] is "101", this means that LRS error and THR empty happen; user can read the LSR register to clear the ID[2] bit and ID[0] bit can also be cleared by reading the IEIR or writing data into THR register.
Level None Highest Second IEIR Bit [2:0] Source of Interrupt 000 None 100 LSR error flags (OE/PE/FE/BI) 010 LSR receiver data ready flag (DR) Interrupt Reset Control
Third
001
LSR flag THR Empty (THRE)
None Reading LSR register to clear ID[2] Reading RBR register to clear ID[1] Reading IEIR register or Writing THR register to clear ID[0]
21.4.Line Control Register
The line control register allows user to configure the asynchronous data transfer format and set the UART function. Reading from the register is allowed to check the current settings of the communication.
Bit 7 BRGE Name Bit 6 SB Bit 5 SP Bit 4 EPS Bit 3 PEN Description Bit 2 STB Bit 1 WLS1 Bit 0 WLS0
Word Length Select "00": word length = 5 "01": word length = 6 WLS[1..0] "10": word length = 7 "11": word length = 8 Stop Bit Length `0': Stop bit length = 1 STB `1': Stop bit length = 1.5 when WLS[1..0]="00", else Stop bit length = 2 Parity Selection "xx0": No Parity "001": odd Parity [SP, EPS, PEN] "011": even Parity "101": Stick Parity 1 "111": Stick parity 0 Set Break When enable the break control bit causes a break condition to be transmitted (SOUT is forced to a logic 0 state). This condition exists until disabled by resetting this bit to SB logic 0. `0': disable break; `1': enable break Baud Rate Generator `0': disable baud rate clock generator BRGE `1': enable baud rate clock generator
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HE80004H SERIES
21.5.Line Status Register
Bit 7 0 Name DR Bit 6 TEMT Bit 5 THRE Bit 4 BI Bit 3 FE Description Receiver Data Ready DR indicates status of RBR. It will be set to logic 1 when RBR data is valid and will be reset to logic 0 when RBR is empty. When line errors (OE/PE/FE/BI) happen, DR will also be set to logic 1 and RBR will be updated to reflect the Data bits portion of the frame. Overrun Error This bit will be set when the next character is transferred into RBR before the previous RBR data is read by the CPU. Even though DR will still be 1 when OE is set to logic 1, the previous frame data stored in RBR which is not read by the CPU is trashed and can`t be recovered. Parity Error This bit will be set to logic 1 only when the Parity is enabled and the Parity bit is not at the logic state it should be. For Even Parity, the Parity bit should be 1 if an odd number of 1s in the Data bits is received; otherwise, the Parity bit should be 0. For Odd Parity, the Parity bit should be 1 if an even number of 1s in the Data bits is received; otherwise, the Parity bit should be 0. For Stick Parity '1', the Parity bit should be 1. For Stick Parity '0', the Parity bit should be 0. Framing Error FE will be reset to logic 0 whenever SIN is sampled high at the center of the first Stop bit, regardless of how many Stop bits the UART is configured to. Bit 2 PE Bit 1 OE Bit 0 DR
OE
PE
FE
Break Interrupt BI will be set to logic 1 whenever SIN is low for longer than the whole frame (the time of Start bit + Data bits + Parity bit + Stop bits), not at the SIN rising edge where BI Break is negated. If SIN is still low after BI is reset to logic 0 by reading LSR, BI will not be set to logic 1 again. Since Break is also a Framing error, FE will also be set to 1 when BI is set. THR Empty THRE will be set to logic 1 whenever THR is empty which indicates that the THRE transmitter is ready to accept new data to transmit. Both THR and TSR are Empty This bit will be set to logic 1 when THRE is set to 1 and the last Data bit in the TSR TEMT is shifted out through SOUT. * The four error flags (OE, PE, FE and BI) of LSR will be reset to logic 0 after a LSR read.
Since the SIN and SOUT of UART pins are shared with PRTD[1..0], users can use the mask option to enable the UART function and select PRTD[1..0] function.
MO_UART
0 1 PRTD[1:0] = I/O Pin PRTD[1:0] = UART Pin
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HE80004H SERIES
22. Extension Register Access
The extension registers can be accessed through the extension port control registers EXTAS and EXTDA. User can read/write the extension register easily and the control timing is generated by hardware automatically. The following code shows how to access the extension registers.
Read Extension Register: LDA #0x00h ; load #0x00h data to A Register STA EXTAS ; store A register data to the extension port address register. LDA EXTDA ; store the extension register (0x00h) data to A Register. Write Extension Register: LDA #0x03h ; load #0x03h data to A Register STA EXTAS ; store A register data to the extension port address register. LDA #0x18h ; load #0x18h data to A Register STA EXTDA ; store A register data to the extension port data register.
23. Summary of Registers and Mask Options
All the registers and mask options used in this chip are listed in the following tables.
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 13H 14H 15H 16H 17H 20H 21H 22H 23H NAME Field Mode RESET TPL Table Pointer Low Byte R/W xxxx xxxx TPH Table Pointer High Byte R/W xxxx xxxx IER INT_EX TB INT1 T1 T2 INT2 R/W --00 0000 T1L Timer 1 Low Byte W xxxx xxxx T1H Timer 1 High Byte W xxxx xxxx T2L Timer 2 Low Byte W xxxx xxxx T2H Timer 2 High Byte W xxxx xxxx SP Stack Pointer R/W 1111 1111 DP RAM Pointer R/W xxxx xxxx OP1 DRDY STOP SLOW INTE T2E T1E Z C R/W 1000 00xx OP2 IDLE PNWK TCWK TBE TBS[3..0] R/W 0xx0 ---PP RAM Page Pointer R/W 0000 0000 PRTC PRTC[7] PRTC[6] PRTC[5] PRTC[4] R/W 1111 ---Reserved PRTD I/O Port D R/W 1111 1111 PWMC PWM Data W 0000 0000 LCDC CLR_GP Reserved BLANK LCDE W xx1x xx10 VOC PWM O/P driver PWME PWM DAC OP R/W x000 0000 PRT14 I/O Port 14 R/W 1111 1111 PRT15 I/O Port 15 R/W 1111 1111 TPP ROM Table Page Pointer R/W 0000 0000 PRT17 I/O Port 17 R/W 1111 1111 EXTAS Extension Port Address Register R/W xxxx xxxx EXTDA Extension Port Data Register R/W xxxx xxxx KEYR0 R RI[1] RI[0] CI[4] CI[3] CI[2] CI[1] CI[0] R/W xxxx xxxx KEYR1 0 RI[1] RI[0] CI[4] CI[3] CI[2] CI[1] CI[0] R/W xxxx xxxx
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Address NAME 24H LCDPS 2BH GRAY16 GRAY0 GRAY1 GRAY2 GRAY3 GRAY4 GRAY5 GRAY6 GRAY7 GRAY8 GRAY9 GRAYA GRAYB GRAYC GRAYD GRAYE GRAYF 2CH PSA1 2DH PSA2 2EH PSA3 30H AC ACL ACH ACP 31H EXMD 32H EXMC
-

HE84G770
HE80004H SERIES
Mode R/W W W W W W W W W W W W W W W W W W R/W R/W R/W R/W AC0 R/W AC8 R/W AC16 R/W R/W DNLD R/W
BUFE
AC7 AC15 AC23 -
Field POWDN PAcc 32 to 16 Gray Level Palette Register Gray Level 0 Mapping Register Gray Level 1 Mapping Register Gray Level 2 Mapping Register Gray Level 3 Mapping Register Gray Level 4 Mapping Register Gray Level 5 Mapping Register Gray Level 6 Mapping Register Gray Level 7 Mapping Register Gray Level 8 Mapping Register Gray Level 9 Mapping Register Gray Level A Mapping Register Gray Level B Mapping Register Gray Level C Mapping Register Gray Level D Mapping Register Gray Level E Mapping Register Gray Level F Mapping Register Physical Page Address Mapping Register for Logical Page 1 Physical Page Address Mapping Register for Logical Page 2 Physical Page Address Mapping Register for Logical Page 3 Download bus address counter AC6 AC5 AC4 AC3 AC2 AC1 AC14 AC13 AC12 AC11 AC10 AC9 AC22 AC21 AC20 AC19 AC18 AC17 Download Bus Data Port WR RD
RESET ---- -100
xxx0 0000 xxx0 0010 xxx0 0100 xxx0 0110 xxx0 1000 xxx0 1010 xxx0 1100 xxx0 1110 xxx1 0000 xxx1 0010 xxx1 0100 xxx1 0110 xxx1 1000 xxx1 1010 xxx1 1100 xxx1 1110 0000 0001 0000 0010 0000 0011 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx x011
Extension registers:
Address 00H 01H 02H 03H 04H 05H 06H 15H 16H 17H Name RBR THR IEIR LCR BRL BRH LSR IRL IRH LDVC Function UART Receiver Buffer UART Transmitter Holding Register THRI RBRI 0 ID2 SP EPS PEN STB UART LSB of Baud Rate Register UART MSB of Baud Rate Register THRE BI FE PE IR PWM Low Duration IR PWM High Duration Mode R R/W R/W R/W R/W R/W R R/W W R/W RESET 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 0xxx xxxx -xxx xxxx x--- ---0
0 BRGE
RLSI SB
ID1 WLS1
ID0 WLS0
0 IROE LVDO
TEMT
OE
DR
-
-
LVDE
Mask Options:
NAME MO_LVRE MO_FXTAL MO_SXTAL MO_FCK/SCKN Value 0 1 0 1 0 1 00 01 Description Low Voltage Reset Disable Low Voltage Reset Enable R/C Oscillator Used for Fast Clock X'tal Oscillator Used for Fast Clock R/C Oscillator Used for Slow Clock X'tal Oscillator Used for Slow Clock Slow Clock Only illegal
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NAME

HE84G770
HE80004H SERIES
Value 10 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0 1 00 01 10 11 00 01 10 11 000
Description Dual Clock Fast Clock Only WDT Disable WDT Enable Open-drain Output Push-pull Output Open-drain Output Push-pull Output Open-drain Output Push-pull Output Open-drain Output Push-pull Output Open-drain Output Push-pull Output PRT14 used as IO pin PRT14 used as LCD pin PRT15 used as IO pin PRT15 used as LCD pin PRT17 used as IO pin PRT17 used as LCD pin LCD Configuration = 32COM x 128SEG LCD Configuration = 48COM x 112SEG LCD Configuration = 64COM x 96SEG LCD Configuration = 80COM x 80SEG LCD Bias= 1/7 LCD Bias= 1/8 LCD Bias= 1/9 LCD Bias= 1/10 Temperature Coefficient of Regulator Voltage = -0.00 / Temperature Coefficient of Regulator Voltage = -0.16 / Temperature Coefficient of Regulator Voltage = -0.22 / Temperature Coefficient of Regulator Voltage = -0.33 / LCD driving current= "Low" LCD driving current= "Medium" LCD driving current= "Medium High" LCD driving current= "High" LCD SGKY[43:24] Used as SEG only LCD SGKY[43:24] Used as SEG/KEY_SCAN Scan Pulse Width = 0.5 SCK Scan Pulse Width = 1.0 SCK Scan Pulse Width = 1.5 SCK Scan Pulse Width = 2.0 SCK Strength of Key Scan = Weakest Strength of Key Scan = Weak Strength of Key Scan = Strong Strength of Key Scan = Strongest Capacitor Selection: C=2P => 4M Hz(R=30k)
MO_WDTE MO_CPP[7:4] MO_DPP[7:0] MO_14PP[7:0] MO_15PP[7:0] MO_17PP[7:0] MO_LIO14[7:0] MO_LIO15[7:0] MO_LIO17[7:0]
MO_COM[1:0]
MO_LBSR[1:0]
MO_TC[1:0]
MO_LOAD[1:0]
MO_LCDKEY
MO_SNCK[1:0]
MO_SCDRV[1:0] MO_RCAP[2:0]
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NAME

HE84G770
HE80004H SERIES
Value 001 010 011 100 101 110 111 0 1 00 01 10 11 0 1 00 01 10 11 0 1 00 01 10 11 0 1 0 1
Description Capacitor Selection: C=4P => 4M Hz(R=17k) Capacitor Selection: C=7P => 4M Hz(R=11k) Capacitor Selection: C=14P => 1M Hz(R=25k) Capacitor Selection: C=20P => 1M Hz(R=18k) Capacitor Selection: C=40P => 500K Hz(R=19k) Capacitor Selection: C=50P => 500K Hz(R=15k) Capacitor Selection: C=60P => 500K Hz(R=13k) 7 bit DAC/PWM Voice Output 8 bit DAC/PWM Voice Output 16 GRAY LEVEL 4 GRAY LEVEL 2 LEVEL(B/W) 2 LEVEL(B/W) Internal MEMORY Used Only External MEMORY Used. Low Voltage Detection Level= 2.4V Low Voltage Detection Level= 2.6V Low Voltage Detection Level= 2.8V Low Voltage Detection Level= 3.0V Default State of the IRO After Reset: Low Default State of the IRO After Reset: High ROM MAP Configuration Option 0 ROM MAP Configuration Option 1 ROM MAP Configuration Option 2 ROM MAP Configuration Option 3 PRTD[1:0] = I/O Pin PRTD[1:0] = UART Pin Disable Internal Charge-pump Enable Internal Charge-pump
MO_8BVOC
MO_GRAY_MODE[1:0]
MO_EXMEM
MO_DLVL[1:0]
MO_IRO
MO_PMODE[1:0]
MO_UART MO_PUMPE
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HE80004H SERIES
24. Absolute Maximum Rating
Item Symbol Rating Condition Supply Voltage VDD -0.5V ~ 4.0V Input Voltage VIN -0.5V ~ VDD+0.5V Output Voltage VO -0.5V ~ VDD+0.5V Operating Temperature TOP 0C ~ 70C Storage Temperature TST -50C ~ 100C
25. Recommended Operating Conditions
Symbol Rating Condition VDD 2.4V ~ 3.6V VIH 0.9 VDD ~ VDD Input Voltage VIL 0.0V ~ 0.1VDD 8M Hz VDD =3.0V Operating Frequency FMAX. 6M Hz VDD =2.4V Operating Temperature TOP 0 C ~ 70 C Storage Temperature TST -50C ~ 100C Item Supply Voltage
26. AC/DC Characteristics
Testing Condition : TEMP=25, VDD=3V10%
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Power consumption NORMAL Mode Current SLOW Mode Current IDLE Mode Current Sleep Mode Current Additional Current if LCD ON I/O specification Input High Voltage Input Low Voltage Input Hysteresis Width Output Source Current Output Sink Current Input Low Current Input Low Current PWM and DAC PWM Output Current
IFAST ISLOW IIDLE ISLEEP ILCD
1 15 10 200 250 300 0.8
1.5 25 20 1 220 275 330
mA A A A A VDD VDD VDD A mA
2M external R/C fast clock 32768 Hz slow clock with LCD disabled 32768 Hz slow clock with LCD disabled LVR and LVD disable LV5=3xLVREG LV5=4xLVREG LV5=5xLVREG Input Pins Input Pins I/O, RSTP_N Threshold = 2/3 VDD (Input from low to high), Threshold = 1/3 VDD (Input from high to low) Output drive high*1, VOH=2.0V Output drive low, VOL=0.4V RSTP_N, VIL = GND, Pull high Internally I/O, VIL=GND, if pull high Internally by user PWM *2 With 32 Loading With 64 Loading With 100 Loading
VIH VIL VHYS IOH IOL1 IIL1 IIL2
0.2 1/3 50 1.0 20 100 10 6 4 14 8 5
A A mA mA mA
IPWM
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DAC Output Current Low voltage Reset LVR detection voltage LVR release voltage IR Output Sink/Source Current LVR power consumption
IVO VDET VRLS IO ILVR
2.5
3 2.2 2.31 20 10
mA Volts Volts mA A
HE84G770
HE80004H SERIES
VO, DAO@ VDD=3V,VO=0~2V, Data =FF
VOL=0.4V, VOH=2.0V When LVR is enabled
Notes: 1. The "Output Source Current" specification is applicable only to the Push-Pull I/O type. 2. This Specification indicates only one PWM driving capability, and there are totally five built-in drivers, user can multiply the actual number of driver to get the total amount of current. (IPWM x N; N=0, 1, 2, 3, 4, 5)
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COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 U14 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5
1uF
27. Application Circuit
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1uF 1uF 1uF 1uF 10uF 10uF
SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 10uF
1 2 3 4 5 6 7 8
SCNI3 10uF 10uF 10pF 4 MHz 260K 1uF 1uF 10pF 0 22pF 12K 100nF 32768Hz HE84G770 22pF 10nF SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 VO DAO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P SXO SXI VX LFR CCK VDD PRTD7 PRTD6 PRTD5 PRTD4 PRTD3 PRTD2 PRTD1 PRTD0 0.1uF 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120
SCNI2
SCNI1
SCNI0
SCNO0 SCNO1 SCNO2 SCNO3
SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11
SCNO17 SCNO18 SCNO19
COM4 COM3 COM2 COM1 COM0 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A LVL5 LVL4 LVL3 LVL2 LVL1 LGS1 LVREG VR12
PRTC7
PRTC6
PRTC5
PRTC4
SGKY 24 SGKY 25 SGKY 26 SGKY 27 : SGKY 41 SGKY 42 SGKY 43
47K
VDD
47K
4.7K
SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 LVL5 LVL5 LVL3 LVL2 LFR CCK REN RWN DCN STBN
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 LVP LVL5 LVL3 LVL2 LFR CCK REN R_WN D_CN STBN
KDGS80H
47K
King Billion Electronics Co., Ltd
59
+ 47uF VDD 2 3.0V 1 PWM VDD RSTP_N 0.1uF VDD SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 R BUZZER 79 78 77 76 75 74 71 73 72 70 69 68 67 66 65 64 63 62 61 60 59 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 This application assumes 80COM X 80SEG configuration, and 80 SEG Extender KDGS80. VO 1K R4 B C11 0.22uF
....
47K
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RSTP_N VDD
30 31 32 33 34 35 36 37 38 39 40
GND RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RES_N VDD
47K
47K
SEG159 SEG158 SEG157 SEG156 SEG155 SEG154 SEG153 SEG152 SEG151 SEG150
41 42 43 44 45 46 47 48 49 50
SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70
SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69
47K
58 57 56 55 54 53 52 51
SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149
Need to fine tuned
E Q1 8050
SEG[0]/PRT17[0] SEG[1]/PRT17[1] SEG[2]/PRT17[2] SEG[3]/PRT17[3] SEG[4]/PRT17[4] SEG[5]/PRT17[5] SEG[6]/PRT17[6] SEG[7]/PRT17[7] SEG[8]/PRT15[0] SEG[9]/PRT15[1] SEG[10]/PRT15[2] SEG[11]/PRT15[3] SEG[12]/PRT15[4] SEG[13]/PRT15[5] SEG[14]/PRT15[6] SEG[15]/PRT15[7] SEG[16]/PRT14[0] SEG[17]/PRT14[1] SEG[18]/PRT14[2] SEG[19]/PRT14[3] SEG[20]/PRT14[4] SEG[21]/PRT14[5] SEG[22]/PRT14[6] SEG[23]/PRT14[7] SGKY24 SGKY25 SGKY26 SGKY27 SGKY28 SGKY29 SGKY30 SGKY31 SGKY32 SGKY33 SGKY34 SGKY35 SGKY36 SGKY37 SGKY38 SGKY39 SGKY40 SGKY41 SGKY42 SGKY43 SEG44/CS1 SEG45/CS0 SEG46/WE SEG47/OE SEG48/A[0] SEG49/A[1] SEG50/A[2] SEG51/A[3] SEG52/A[4] SEG53/A[5] SEG54/A[6] SEG55/A[7] SEG56/A[8] SEG57/A[9] SEG58/A[10] SEG59/A[11] SEG60/A[12] SEG61/A[13] SEG62/A[14] SEG63/A[15] SEG64/A[16] SEG65/A[17] SEG66/A[18] SEG67/A[19] SEG68/A[20] SEG69/A[21] SEG70/A[22] SEG71/A[23] SEG72/D[0] SEG73/D[1] SEG74/D[2] SEG75/D[3] SEG76/D[4] SEG77/D[5] VDD PWM VDD C PWM IRO /CS3 /CS2 VDD PRTC7 PRTC6 PRTC5 PRTC4 CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 SEG78/D[6] SEG79/D[7] CMSG79 CMSG78 CMSG77 CMSG76 CMSG75 CMSG74 CMSG73 CMSG72 CMSG71 CMSG70 CMSG69 CMSG68 CMSG67 CMSG66 CMSG65 CMSG64 CMSG63 CMSG62 CMSG61
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 COM4 COM3 COM2 COM1 COM0 LCAP2B LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A LVL5 LVL4 LVL3 LVL2 LVL1 LGS1 LVREG VR12 GND VO DAO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P SXO SXI VX OLFR OCCK VDD PRTD[7]/INT2//WKUP[5] PRTD[6]/INT1/WKUP[4] PRTD[5]/WKUP[3] PRTD[4]/WKUP[2] PRTD[3]/WKUP[1] PRTD[2]/WKUP[0] PRTD[1]/SIN PRTD[0]/SOUT GND_PWM PWM IRO CS3 CS2 VDD_RAM PRTC[7]/SCNI[3] PRTC[6]/SCNI[2] PRTC[5]/SCNI[1] PRTC[4]/SCNI[0] CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SGKY24 SGKY25 SGKY26 SGKY27 SGKY28 SGKY29 SGKY30 SGKY31 SGKY32 SGKY33 SGKY34 SGKY35 SGKY36 SGKY37 SGKY38 SGKY39 SGKY40 SGKY41 SGKY42 SGKY43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77
131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 SEG78 SEG79 CMSG79 CMSG78 CMSG77 CMSG76 CMSG75 CMSG74 CMSG73 CMSG72 CMSG71 CMSG70 CMSG69 CMSG68 CMSG67 CMSG66 CMSG65 CMSG64 CMSG63 CMSG62 CMSG61
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G770
HE80004H SERIES
Version:V1.1
King Billion Electronics Co., Ltd

Note: Options for system configuration of LCD Display, Osc. and external memory.
Intel NOR FLASH COMXSEG CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 CMSG64 CMSG65 CMSG66 CMSG67 CMSG68 CMSG69 CMSG70 CMSG71 CMSG72 CMSG73 CMSG74 CMSG75 CMSG76 CMSG77 CMSG78 CMSG79 32X128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 48X112 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 64X96 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 80X80 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 Ext. Bus Interface A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 MB EPROM A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS VCC A18 A17 A14 A13 A8 A9 A11 OE/VPP A10 CE Q7 Q6 Q5 Q4 Q3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A18 A17 A14 A13 A8 A9 A11 A10 CS0 Q7 Q6 Q5 Q4 Q3 VDD A16 A15 A14 A13 A12 A11 A9 A8 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A16 A15 A14 A13 A12 A11 A9 A8 WE RP VPP WP A18 A7 A6 A5 A4 A3 A2 A1 28F320-TSOP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A20 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 Q7 Q6 Q5 Q4 VDD 512KB x 8 SRAM A11 A9 A8 A13 WE A17 A15 VDD A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 LP62S4096-TSOP
HE84G770
HE80004H SERIES
SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79
CS1 CS0 WE OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0.1uF
M27C801 16 MB EPROM A19 A18 A8 A7 A6 A5 A4 A3 A2 A1 CS1 D0 Q1 Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 M27C160 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BY TE VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
A18 A7 A6 A5 A4 A3 A2 A1
A17 GND A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE GND CE A0
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 A20 A19 A10 DQ7 DQ6 DQ5 DQ4
DQ3 DQ2 DQ1 DQ0 OE CE A0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
OE A10 CS1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CS3 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
SXI SXI
x3 charge pump config. 1uF 260K R 1uF SXO 10uF 10uF RC Osc. 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B
x4 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B LCAP5A LCAP4A 1uF 1uF 1uF LCAP3A LCAP2A LCAP1A
x5 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B LCAP5A 1uF 1uF 1uF 1uF LCAP4A LCAP3A LCAP2A LCAP1A
x6 charge pump config. 1uF 260K 1uF 10uF 10uF 10uF 10uF 10uF VR12 GS1 VREG LVL5 LVL4 LVL3 LVL2 LVL1 LCAP2B LCAP1B 1uF 1uF 1uF 1uF 1uF LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A
SXO Crystal Osc.
FXI FXI R1 51K 1uF FXO Crystal Osc. RC Osc. 1uF
LCAP1B LCAP5A LCAP4A LCAP3A LCAP2A LCAP1A
October 31, 2003
60
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd

HE84G770
HE80004H SERIES
28. Important Note
1. Please note that ICE is different from IC which is your target chip. The ICE is a superset of HE80004H series IC, but each IC is a subset of ICE. Don't use any hardware resource that your target chip doesn't have them, especially RAM and register. KBIDS and compiler can't prevent user from using some hardware resources that don't exist in your target chip. To access "Data ROM", users must update TPP first, TPH, and then TPL. Only follow this order, the pre-charge circuit of ROM will work correctly. The 5s waiting is also necessary before LDV instruction is executed since Data ROM is a low speed ROM. User can't emulate this accessing process in ICE, so 5s delay should be added by firmware. Please bond the TSTP_P, RSTP_N and PRTD [7:0] with test points on PCB (can be soldered and probed) as you can, then some testing can be performed on PCB when it's necessary. The TSTP_P is suggested to connect to ground by a 0 ohm resistor. The following figure is an example (Testing point with through hole).
The LV5 must be lower than 12 Volt; otherwise the chip may be damaged.
2.
3.
4.
29. Updated History
Version V1.0
V1.1
Date Revised History 7/22/03 New Released 1. Modify the 7-bit DAC block diagram 10/31/03 2. Change the product name from HE84G770H to HE84G770
October 31, 2003
61
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.

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